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HD61830/HD61830B
LCDC (LCD Timing Controller)
ADE-207-275(Z) '99.9 Rev. 0.0 Description
The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal driving signals. It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on liquid crystal display and a character mode in which characters are displayed by storing character codes in the external RAM and developing them into the dot patterns with the internal character generator ROM. Both modes can be provided for various applications. The HD61830/HD61830B is produced by the CMOS process. Thus, combined with a CMOS microcontroller it can complete a liquid crystal display device with lower power dissipation.
Features
* Dot matrix liquid crystal graphic display controller * Display control capacity Graphic mode: 512k dots (216 bytes) Character mode: 4096 characters (212 characters) * Internal character generator ROM: 7360 bits 160 types of 5 x 7 dot characters 32 types of 5 x 11 dot characters Total 192 characters Can be extended to 256 characters (4 kbytes max.) with external ROM
1
HD61830/HD61830B
* Interfaces to 8-bit MPU * Display duty cycle (can be selected by a program) Static to 1/128 duty cycle * Various instruction functions Scroll, cursor on/off/blink, character blink, bit manipulation * Display method: Selectable A or B types * Internal oscillator (with external resistor and capacitor) HD61830 * Operating frequency 1.1 MHz HD61830 2.4 MHz HD61830B * Low power dissipation * Power supply: Single +5 V 10% * CMOS process
2
HD61830/HD61830B
Differences between Products HD61830 and HD61830B
HD61830 Oscillator Operating frequency Pin arrangement and signal name Package marking to see figure Internal or external 1.1 MHz Pin 6: C Pin 7: R Pin 9: CPO
A
HD61830B External only 2.4 MHz Pin 6: CE Pin 7: OE Pin 9: NC
B
Package Marking
3D13 A HD61830A00 JAPAN
Lot No.
3D13 B HD61830B00 JAPAN
Lot No.
Ordering Information
Type No. HD61830A00H HD61830B00H Package 60-pin plastic QFP (FP-60)
3
HD61830/HD61830B
Pin Arrangement
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 56 MA9 55 54 53 52 51 50 49 48 47 FP-60 (Top view) 46 45 44 43 42 41 40 39 38 37 24 25 26 27 28 29 30 31 32 33 34 35 36 MB 5
4
3
2
1
60
59
58
57
MA10 MA11 MA12 MA13 MA14 MA15 D2 D1 CL2 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 MD0 MD1
(CE) C (OE) R CR (NC) CPO FLM CL1 SYNC WE RES CS E R/W RS MA GND DB7 DB6 DB5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MD7
MD6
MD5
MD4
MD3
DB4
DB3
DB2
DB1
DB0
( ) is for HD61830B
4
MD2
VCC
HD61830/HD61830B
Terminal Functions
Symbol DB0-DB7 CS R/W RS E CR C R CPO CE OE Pin Number 28-21 15 17 18 16 8 6 7 9 6 7 I/O I/O I I I I I -- -- O O O Function Data bus: Three-state I/O common terminal Data is transferred to MPU through DB0 to DB7. Chip select: Selected state with CS = 0 Read/Write:R/W = 1: MPU HD61830 R/W = 0: MPU HD61830 Register select: RS = 1: Instruction register RS = 0: Data register Enable: Data is written at the fall of E Data can be read while E is 1 CR oscillator (HD61830), External clock input (HD61830B) CR oscillator to capacitor (HD61830 only) CR oscillator to resistor (HD61830 only) Clock signal for HD61830 in slave mode (HD61830 only) Chip enable (HD61830B only) CE = 0: Chip enables make external RAM in active Output enable (HD61830B only) OE = 1: Output enable informs external RAM that HD61830B requires data bus
NC MA0-MA15
9 4-1, 60-49
Open Unused terminal. Don't connect any wires to this terminal (HD61830B only) O External RAM address output In character mode, the line code for external CG is output through MA12 to MA15 (0: Character 1st line, F: Character 16th line) Display data bus: Three-state I/O common terminal ROM data input: Dot data from external character generator is input Write enable: Write signal for external RAM Display data shift clock for LCD drivers Display data latch signal for LCD drivers Frame signal for display synchronization Signal for converting liquid crystal driving signal into AC, A type Signal for converting liquid crystal driving signal into AC, B type Display data serial output D1: For upper half of screen D2: For lower half of screen Synchronous signal for parallel operation Three-state I/O common terminal (with pull-up MOS) Master: Synchronous signal is output Slave: Synchronous signal is input Reset: Reset = 0 results in display off, slave mode and Hp = 6
MD0-MD7 RD0-RD7 WE CL2 CL1 FLM MA MB D1 D2 SYNC
37-30 45-38 13 46 11 10 19 5 47 48 12
I/O I O O O O O O O
I/O
RES
14
I
5
Multiplexer
I/O interface circuit
6
SYNC CL1 MA MB FLM (CE) (OE) WE Dot counter (DC) RAM * MD0-MD7 Dot registers (DR) 8 4 Character generator ROM (CGROM) 8 6 8 Cursor signal generator Control signal Line address counter Refesh address 16 counter (1) (RAC1) Refesh address 16 counter (2) (RAC2) Cursor address 16 counter (CAC) Extended external ROM RD0-RD7 Multiplexer Mode control register (MCR) Control signal Parallel/serial converter Oscillator circuit D1 Parallel/serial converter D2 Cf (CL2) Rf CPO (CR) * When extended external ROM is used, MA0-MA11 are applied to RAM, MA12 -MA15 are applied to extended external ROM. ( ) is for HD61830B
Block Diagram
8
HD61830/HD61830B
DB0-DB7
CS E RS R/W RES
Data input register (DIR)
Data output register (DOR)
4
Busy flag (BF)
Instruction register (IR)
Oscillator circuit
CL2
HD61830/HD61830B
Block Functions
Registers The HD61830/HD61830B has the five types of registers: instruction register (IR), data input register (DIR), data output register (DOR), dot registers (DR), and mode control register (MCR). The IR is a 4-bit register that stores the instruction codes for specifying MCR, DR, a start address register, a cursor address register, and so on. The lower order 4 bits DB0 to DB3 of data buses are written in it. The DIR is an 8-bit register used to temporarily store the data written into the external RAM, DR, MCR, and so on. The DOR is an 8-bit register used to temporarily store the data read from the external RAM. Cursor address information is written into the cursor address counter (CAC) through the DIR. When the memory read instruction is set in the IR (latched at the falling edge of E signal), the data of external RAM is read to DOR by an internal operation. The data is transferred to the MPU by reading the DOR with the next instruction (the contents of DOR are output to the data bus when E is at the high level). The DR are registers used to store dot information such as character pitches and the number of vertical dots, and so on. The information sent from the MPU is written into the DR via the DIR. The MCR is a 6-bit register used to store the data which specifies states of display such as display on/off and cursor on/off/blink. The information sent from the MPU is written in it via the DIR. Busy Flag (BF) The busy flag = 1 indicates the HD61830 is performing an internal operation. Instructions cannot be accepted. As shown in Control Instruction, read busy flag, the busy flag is output on DB7 under the conditions of RS = 1, R/W = 1, and E = 1. Make sure the busy flag is 0 before writing the next instruction. Dot Counters (DC) The dot counters are counters that generate liquid crystal display timing according to the contents of DR.
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HD61830/HD61830B
Refresh Address Counters (RAC1/RAC2) The refresh address counters, RAC1 and RAC2, control the addresses of external RAM, character generator ROM (CGROM), and extended external ROM. The RAC1 is used for the upper half of the screen and the RAC2 for the lower half. In the graphic mode, 16-bit data is output and used as the address signal of external RAM. In the character mode, the high order 4 bits (MA12-MA15) are ignored. The 4 bits of line address counter are output instead and used as the address of extended ROM. Character Generator ROM The character generator ROM has 7360 bits in total and stores 192 types of character data. A character code (8 bits) from the external RAM and a line code (4 bits) from the line address counter are applied to its address signals, and it outputs 5-bit dot data. The character font is 5 x 7 (160 characters) or 5 x 11 (32 characters). The use of extended ROM allows 8 x 16 (256 characters max.) to be used. Cursor Address Counter The cursor address counter is a 16-bit counter that can be preset by instruction. It holds an address when the data of external RAM is read or written (when display dot data or a character code is read or written). The value of the cursor address counter is automatically increased by 1 after the display data is read or written and after the set/clear bit instruction is executed. Cursor Signal Generator The cursor can be displayed by instruction in character mode. The cursor is automatically generated on the display specified by the cursor address and cursor position. Parallel/Serial Conversion The parallel data sent from the external RAM, character generator ROM, or extended ROM is converted into serial data by two parallel/serial conversion circuits and transferred to the liquid crystal driver circuits for upper screen and lower screen simultaneously.
8
HD61830/HD61830B
Display Control Instructions Display is controlled by writing data into the instruction register and 13 data registers. The RS signal distinguishes the instruction register from the data registers. 8-bit data is written into the instruction register with RS = 1, and the data register code is specified. After that, the 8-bit data is written in the data register and the specified instruction is executed with RS = 0. During the execution of the instruction, no new instruction can be accepted. Since the busy flag is set during this, read the busy flag and make sure it is 0 before writing the next instruction. 1. Mode Control: (Execution time: 4 s) Code H'00 (hexadecimal) written into the instruction register specifies the mode control register.
Register Instruction reg. Mode control reg. R/W 0 0 RS 1 0 DB7 0 0 DB6 0 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Mode data
DB5 1/0
DB4 1/0
DB3 0 0 1 1 0 0 1 1 0
DB2 0 1 0 1 0 1 0 1 0
DB1 0
DB0 0
Cursor/blink Cursor off Cursor on Cursor off, character blink Cursor blink
CG
Graphic/character display Character display (Character mode)
1
Cursor off Cursor on Cursor off, character blink Cursor blink
External CG
Graphic mode
1
0
Graphic/character mode
Display ON/OFF
Master/slave
1: Master mode 0: Slave mode 1: Display ON 0: Display OFF
Ext./Int. CG
Cursor
Blink
Internal CG
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HD61830/HD61830B
2. Set Character Pitch: (Execution time: 4 s) Vp indicates the number of vertical dots per character. The space between the vertically-displayed characters is included in the determination. This value is meaningful only during character display (in the character mode) and becomes invalid in the graphic mode. H p indicates the number of horizontal dots per character in display, including the space between horizontally-displayed characters. In the graphic mode, the Hp indicates the number of bits of 1-byte display data to be displayed. There are three Hp values (Table 1).
Register Instruction reg. Character pitch reg. R/W 0 0 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 0 DB2 0 DB1 0 DB0 1
(Vp - 1) binary
(Hp - 1) binary
Table 1
Hp 6 7 8
Hp Values
DB2 1 1 1 DB1 0 1 1 DB0 1 0 1 Horizontal Character Pitch 6 7 8
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HD61830/HD61830B
3. Set Number of Characters: (Execution time: 4 s) HN indicates the number of horizontal characters in the character mode or the number of horizontal bytes in the graphic mode. If the total sum of horizontal dots on the screen is taken as n, n = Hp x HN HN can be set to an even number from 2 to 128 (decimal).
Register Instruction reg. Number-of-characters reg. R/W 0 0 RS 1 0 DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
(HN - 1) binary
4. Set Number of Time Divisions (Inverse of Display Duty Ratio): (Execution time: 4 s) NX indicates the number of time divisions in multiplex display. 1/NX is the display duty ratio. A value of 1 to 128 (decimal) can be set to NX.
Register Instruction reg. Number-of-time-divisions reg. R/W 0 0 RS 1 0 DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
(NX - 1) binary
5. Set Cursor Position: (Execution time: 4 s) Cp indicates the position in a character where the cursor is displayed in the character mode. For example, in 5 x 7 dot font, the cursor is displayed under a character by specifying C p = 8 (decimal). The cursor horizontal length is equal to the horizontal character pitch H p. A value of 1 to 16 (decimal) can be set to Cp. If a smaller value than the vertical character pitch Vp is set (Cp Vp), and a character overlaps with the cursor, the cursor has higher priority of display (at cursor display on). If Cp is greater than Vp, no cursor is displayed. The cursor horizontal length is equal to Hp.
Register Instruction reg. Cursor position reg. R/W 0 0 RS 1 0 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 0 DB2 1 DB1 0 DB0 0
(Cp - 1) binary
11
HD61830/HD61830B
6. Set Display Start Low Order Address: (Execution time: 4 s) Cause display start addresses to be written in the display start address registers. The display start address indicates a RAM address at which the data displayed at the top left end on the screen is stored. In the graphic mode, the start address is composed of high/low order 16 bits. In the character display, it is composed of the lower 4 bits of high order address (DB3-DB0) and 8 bits of low order address. The upper 4 bits of high order address are ignored.
Register Instruction reg. Display start address reg. (low order byte) R/W 0 0 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 0
(Start low order address) binary
Set Display Start High Order Address
Register Instruction reg. Display start address reg. (high order byte) R/W 0 0 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 1
(Start high order address) binary
7. Set Cursor Address (Low Order) (RAM Write Low Order Address): (Execution time: 4 s) Cause cursor addresses to be written in the cursor address counters. The cursor address indicates an address for sending or receiving display data and character codes to or from the RAM. That is, data at the address specified by the cursor address are read/written. In the character mode, the cursor is displayed at the character specified by the cursor address. A cursor address consists of the low-order address (8 bits) and the high-order address (8 bits). Satisfy the following requirements setting the cursor address (Table 2). The cursor address counter is a 16-bit up-counter with set and reset functions. When bit N changes from 1 to 0, bit N + 1 is incremented by 1. When setting the low order address, the LSB (bit 1) of the high order address is incremented by 1 if the MSB (bit 8) of the low order address changes from 1 to 0. Therefore, set both the low order address and the high order address as shown in the Table 2.
Register Instruction reg. Cursor address counter (low order byte) R/W 0 0 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 1 DB0 0
(Cursor low order address) binary
12
HD61830/HD61830B
Set Cursor Address (High Order) (RAM Write High Order Address)
Register Instruction reg. Cursor address counter (high order byte) R/W 0 0 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
(Cursor high order address) binary
Table 2
Condition
Cursor Address Setting
Requirement Set the low order address and then set the high order address.
When you want to rewrite (set ) both the low order address and the high order address.
When you want to rewrite only the low order address. Do not fail to set the high order address again after setting the low order address. When you want to rewrite only the high order address. Set the high order address. You do not have to set the low order address again.
13
HD61830/HD61830B
8. Write Display Data: (Execution time: 6 s) After the code $"0C" is written into the instruction register with RS = 1, 8-bit data with RS = 0 should be written into the data register. This data is transferred to the RAM specified by the cursor address as display data or character code. The cursor address is increased by 1 after this operation.
Register Instruction reg. RAM R/W 0 0 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 1 DB1 0 DB0 0
MSB (pattern data, character code) LSB
9. Read Display Data: (Execution time: 6 s) Data can be read from the RAM with RS = 0 after writing code $"0D" into the instruction register. Figure 1 shows the read procedure. This instruction outputs the contents of data output register on the data bus (DB0 to DB7) and then transfers RAM data specified by the cursor address to the data output register, also increasing the cursor address by 1. After setting the cursor address, correct data is not output at the first read but at the second one. Thus, make one dummy read when reading data after setting the cursor address.
Register Instruction reg. RAM R/W 0 1 RS 1 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 1 DB1 0 DB0 1
MSB (pattern data, character code) LSB
CS E R/W RS DB B 0A NL B OB
Cursor address set mode
NU
B
0D
Data read mode
*
Dummy read
B
(N)
B
(N+1)
Busy Cursor check address set mode
Cursor Busy low check order address write
Cursor Busy high check order address write
Busy N check address data read
Busy N + 1 check address data read
Cursor address Data output register
NL
N
N+1
N+2
N+3
N address data N + 1 address data N + 2 ...
Figure 1 Read Procedure
14
HD61830/HD61830B
10. Clear Bit: (Execution time: 36 s) The clear/set bit instruction sets 1 bit in a byte of display data RAM to 0 or 1, respectively. The position of the bit in a byte is specified by NB and RAM address is specified by cursor address. After the execution of the instruction, the cursor address is automatically increased by 1. NB is a value from 1 to 8. NB = 1 and NB = 8 indicates LSB and MSB, respectively.
Register Instruction reg. Bit clear reg. R/W 0 0 RS 1 0 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 1 0 DB2 1 DB1 1 DB0 0
(NB - 1) binary
Set Bit
Register Instruction reg. Bit set reg. R/W 0 0 RS 1 0 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 1 0 DB2 1 DB1 1 DB0 1
(NB - 1) binary
11. Read Busy Flag: (Execution time: 0 s) When the read mode is set with RS = 1, the busy flag is output to DB7. The busy flag is set to 1 during the execution of any of the other instructions. After the execution, it is set to 0. The next instruction can be accepted. No instruction can be accepted when busy flag = 1. Before executing an instruction or writing data, perform a busy flag check to make sure the busy flag is 0. When data is written in the register (RS = 1), no busy flag changes. Thus, no busy flag check is required just after the write operation into the instruction register with RS = 1. The busy flag can be read without specifying any instruction register.
Register Busy flag R/W 1 RS 1 DB7 1/0 DB6 DB5 DB4 DB3 * DB2 DB1 DB0
15
HD61830/HD61830B
Hp RD0 RD7
Vp
NX
CURA STA
HN (digit)
Symbol Hp HN
Name Horizontal character pitch Number of horizontal characters
Meaning Horizontal character pitch Number of horizontal characters per line (number of digits) in the character mode or number of bytes per line in the graphic mode Vertical character pitch Line number on which the cursor can be displayed Inverse of display duty ratio
Cp
Value 6 to 8 dots 2 to 128 digits (an even number)
Vp Cp NX
Vertical character pitch Cursor position Number of time divisions
1 to 16 dots 1 to 16 lines 1 to 128 lines
Note: If the number of vertical dots on the screen is m, and the number of horizontal dots is n, 1/m = 1/NX = display duty ratio n = Hp x HN, m/Vp = Number of display lines Cp Vp
Figure 2 Display Variables
16
Display Mode
Display Mode Hp b7 b6 b5 b4 b3 b2 b1 b0 A B C
Display Data from MPU RAM
Liquid Crystal Display Panel
Character display
Character code (8 bits)
01000001 Start address 01000010
Hp: 6, 7, or 8 dots
Graphic b7 b6 b5 b4 b3 b2 b1 b0
Display pattern (8 bits)
b0
b7
Hp
8 dots 01010101 Start address 11111111
8 dots
Hp: 8 dots
HD61830/HD61830B
17
HD61830/HD61830B
Internal Character Generator Patterns and Character Codes
Lower 4 bits Higher 4 bits
0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111
xxxx0000
xxxx0001
xxxx0010
xxxx0011
xxxx0100
xxxx0101
xxxx0110
xxxx0111
xxxx1000
xxxx1001
xxxx1010
xxxx1011
xxxx1100
xxxx1101
xxxx1110
xxxx1111
18
HD61830/HD61830B
Example of Correspondence between External CGROM Address Data and Character Pattern
8 x 8 Dot Font
A10 A9 A8 A7 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1
A6 A5 A4 A3 A2 A1 A0 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
8 x 16 Dot Font
A11 0 0 A10 0 0 A9 0 0 A8 0 1 A7 A6 A5 A4 A3 A2 A1 A0 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0
0
0
0
0 0 0 0 0 0 0 0 0 0
1110 1111 0000
19
HD61830/HD61830B
Example of Configuration
Graphic Mode or Character Mode (1) (Internal Character Generator)
MPU
HD61830 HD61830B MD0-MD7
Liquid crystal display module
MA0 -MA15 at graphic mode, MA0 -MA11 at character mode RAM
Character Mode (2) (External Character Generator)
HD61830 HD61830B MA12- RD0-RD7 MA15 ROM MA0-MA11
MPU
Liquid crystal display module
MD0 - MD7
RAM
20
HD61830/HD61830B
Parallel Operation (HD61830)
(Master) MPU HD61830 (1) CS CPO SYNC RAM CR SYNC HD61830 (2) CS (Slave) RAM Liquid crystal Liquid crystal display module (1) display module (2) Driving both of two module by same common signal
Parallel Operation (HD61830B)
(Master) MPU HD61830B (1) CS SYNC RAM Liquid crystal Liquid crystal display module (1) display module (2) Driving both of two module by same common signal
SYNC HD61830B (2) CS (Slave) RAM
21
HD61830/HD61830B
HD61830 Application (Character Mode, External CG, Character Font 8 x 8)
HD6800 A0 A12 A13 A14 A15 VMA D0 to D7 o2 R/W RS HD61830 WE MA0 to MA10 MA11 MA12 to MA14 MA15 MD0 to MD7 A0-A2 RD0 to RD7 D1 FLM MB CL1 CL2 D2 MA CR C +5 V GND -5 V R D0 to D7 A3 -A10 OE CE D1 FLM M CL1 CL2 D2 +5 V GND -5 V V0 ROM HN462716 WE OE A0 RAM (1) HM6116 to A10 CS WE RAM (2) A0 HM6116 to A10 CS OE
CS
DB0 to DB7 E R/W
Open VCC
SYNC CPO RES R C
LCD module
Open
HD61830 Application (Graphic Mode)
DB0-DB7 HD6800 MPU CS E RS R/W RES HD61830 controller
D1 D2 CL1, CL2 MB, FLM Common driver
Segment driver
Segment driver
MA0 - MA15 MD0-MD7 WE
LCD
RAM 16 kbits CMOS
Segment driver
Segment driver
GND VDD (5 V) VEE (-5 V)
V1 - V6 Power supply for liquid crystal display drive
22
HD61830/HD61830B
HD61830B Application (Character Mode, External CG, Character Font 8 x 8)
HD6303 A0 A1 to A15 Decoder D0 to D7 E R/W DB0 to DB7 E R/W RS CS HD61830B WE MA0 to MA10 OE CE MA11 MA12 to MA15 MD0 to MD7 RD0 to RD7 D1 FLM MB CL1 CL2 D2 MA OE WE D0 A0 RAM (1) to to HM6116 D7 A10 CS WE A0 RAM (2) HM6116 to A10 OE D0 to D7 CS
A0-A3 D0 to D7
A4-A11 OE CE D1 FLM M CL1 CL2 D2 +5 V GND -5 V V0
ROM HN482732A
Open VCC External clock
SYNC RES CR
LCD module
Open
+5 V GND -5 V
HD61830B Application (Graphic Mode)
DB0 -DB7 HD6303 MPU CS E RS R/W RES HD61830B controller
D1 D2 CL1, CL2 MB, FLM Common driver MA0 - MA15
Segment driver
Segment driver
LCD
OE
MD0-MD7
WE
CE
RAM 16 kbits CMOS
Segment driver
Segment driver
GND VDD (5 V) VEE (-5 V)
V1 - V6 Power supply for liquid crystal display drive
23
HD61830/HD61830B
HD61830 Absolute Maximum Ratings
Item Supply voltage Terminal voltage Operating temperature Storage temperature Symbol VCC VT Topr Tstg Value -0.3 to +0.7 -0.3 to VCC +0.3 -20 to +75 -55 to +125 Unit V V C C Notes 1, 2 1, 2
Notes: 1. All voltages are referenced to GND = 0 V. 2. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed. We strongly recommend that you use the LSIs within electrical characteristic limits for normal operation, because use beyond these conditions will cause malfunction and poor reliability.
24
HD61830/HD61830B
HD61830 Electrical Characteristics (VCC = 5 V 10%, GND = 0 V, T a = -20 to +75C)
Item Input high voltage (TTL) Input low voltage (TTL) Input high voltage Input high voltage (CMOS) Input low voltage (CMOS) Output high voltage (TTL) Output low voltage (TTL) Output high voltage (CMOS) Output low voltage (CMOS) Input leakage current Three-state leakage current Power dissipation (1) Power dissipation (2) Internal clock operation (Clock oscillation frequency) External clock operation (External clock operating frequency) External clock duty External clock rise time External clock fall time Pull-up current Symbol Min VIH VIL VIHR VIHC VILC VOH VOL VOHC VOLC I IN I TSL PW 1 PW 2 f osc f cp Duty t rcp t fcp I PL 2.2 0 3.0 0.7 VCC 0 2.4 0 Typ -- -- -- -- -- -- -- Max VCC 0.8 VCC VCC 0.3 VCC VCC 0.4 VCC 0.4 5 10 15 30 600 1100 52.5 0.05 0.05 20 Unit V V V V V V V V V A A mW mW kHz kHz % s s A VIN = GND -I OH = 0.6 mA I OL = 1.6 mA -I OH = 0.6 mA I OL = 0.6 mA VIN = 0 - VCC Test Condition Notes 1 2 3 4 4 5 5 6 6 7
VCC - 0.4 -- 0 -5 -10 -- -- 400 100 47.5 -- -- 2 -- -- -- 10 20 500 500 50 -- -- 10
VOUT = 0 - VCC 8 CR oscillation f osc = 500 kHz External clock f cp = 1 MHz 9 9
Cf = 15 pF 5% 10 Rf = 39 k 2% 11 11 11 11 12
Notes: The I/O terminals have the following configuration: 1. Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES. 2. Applied to input terminals and I/O common terminals, except terminals SYNC and CR. 3. Applied to terminal RES. 4. Applied to terminals SYNC and CR. 5. Applied to terminals DB0-DB7, WE, MA0-MA15, and MD0-MD7. 6. Applied to terminals SYNC, CP0, FLM, CL1, CL2, D1, D2, MA, and MB. 7. Applied to input terminals. 8. Applied to I/O common terminals. However, the current which flows into the output drive MOS is excluded.
25
HD61830/HD61830B
9. The current which flows into the input and output circuits is excluded. When the input of CMOS is in the intermediate level, current flows through the input circuit, resulting in the increase of power supply current. To avoid this, input must be fixed at high or low. The relationship between the operating frequency and the power dissipation is given below. PW (mW) 50 Max 40 30 20 10 0 Typ
250
500
750
1000
1250
1500
fOSC (kHz) 10. Applied to the operation of the internal oscillator when oscillation resistor Rf and oscillation capacity Cf are used. R Rf Cf CR The relationship among oscillation frequency, R f and Cf is given below. fOSC (kHz) 800 600 400 200 0 Cf = 10 pF Cf = 15 pF 40 60 80 100 120 140 160 180 Rf (k) Ta = 25C, VCC = 5 V C Cf = 15 pF 5% Rf = 39 k 2% (when fOSC = 500 kHz typ)
26
HD61830/HD61830B
11. Applied to external clock operation. Th Open Open Oscillator R C CR Duty cycle = trcp 12. Applied to SYNC, DB0-DB7, and RD0-RD7. tfcp Th x 100% Th + TI 0.7 VCC 0.5 VCC 0.3 VCC TI
27
HD61830/HD61830B
Input Terminal Applicable terminal: CS, E, RS, R/W, RES, CR (without pull-up MOS)
VCC PMOS
NMOS
Applicable terminal: RD0-RD7 (with pull-up MOS)
VCC PMOS (Pull-up MOS) NMOS VCC PMOS
28
HD61830/HD61830B
Output Terminal Applicable terminal: CL1, CL2, MA, MB, FLM, D1, D2, WE, CPO, MA0-MA15
VCC PMOS
NMOS
I/O Common Terminal Applicable terminal: DB0-DB7, SYNC, MD0-MD7 (MD0-MD7 have no pull-up MOS)
VCC PMOS (Pull-up MOS) NMOS PMOS Data Input circuit NMOS VCC PMOS
VCC Enable
Output circuit (Three state)
29
HD61830/HD61830B
Timing Characteristics
HD61830 MPU Interface (V CC = 5 V 10%, GND = 0 V, Ta = -20 to +75C)
Item Enable cycle time Enable pulse width High level Low level Enable rise time Enable fall time Setup time Data setup time Data delay time Data hold time Address hold time Output data hold time Symbol t CYC t WEH t WEL t Er t Ef t AS t DSW t DDR t DHW t AH t DH Min 1.0 0.45 0.45 -- -- 140 225 -- 10 10 20 Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 25 25 -- -- 225 -- -- -- Unit s s s ns ns ns ns ns * ns ns ns
Note: * The following load circuit is connected for specification:
tCYC tWEH E 2.2 V 0.8 V tAS CS, R/W, RS 2.2 V 0.8 V tDSW DB0-DB7 (MPUHD61830) 2.2 V 0.8 V tDDR DB0-DB7 (MPUHD61830) VCC D1 Test point D2 R C D3 D4 RL = 2.4 k R = 11 k C = 130 pF (C includes jig capacitance) Diodes D1 to D4 : 1S2074 H RL 2.4 V 0.4 V tDH tDHW tEr tEf tWEL
tAH
30
HD61830/HD61830B
HD61830 External RAM and ROM Interface (VCC = 5 V 10%, GND = 0 V, Ta = -20 to +75C)
Item SYNC delay time SYNC pulse width CPO cycle time CPO pulse width High level Low level MA0 to MA15 refresh delay time MA0 to MA15 write address delay time MD0 to MD7 write data delay time MD0 to MD7, RD0 to RD7 setup time Memory address setup time Memory data setup time WE delay time WE pulse width (low level) Low level Symbol t DSY t WSY t CCPO t WCPOH t WCPOL t DMAR t DMAW t DMDW t SMD t SMAW t SMDW t DWE t WWE Min -- 900 900 450 450 -- -- -- 900 250 250 -- 450 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max 200 -- -- -- -- 200 200 200 -- -- -- 200 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
SYNC tDSY CPO
1 V 2 CC tWSY
tCCPO 1 V 2 CC tWCPOL tWCPOH 2.4 V 0.4 V
MA0-MA15 tDMAR MD0-MD7
tDMAR * 2.2 V 0.8 V tSMD * 2.2 V 0.8 V *
tDMAW
tSMAW 2.4 V 0.4 V tSMDW
tDMDW
RD0-RD7
2.2 V 0.8 V tSMD * 2.4 V 0.4 V tDWE tWWE
WE
Notes: 1. No load is applied to all the output terminals. 2. "*" indicates the delay time of RAM and ROM.
31
HD61830/HD61830B
HD61830 LCD Driver Interface (VCC = 5 V 10%, GND = 0 V, Ta = -20 to +75C)
Item Clock pulse width (high level) Clock delay time Clock cycle time Clock pulse width High level Low level MA, MB delay time FLM delay time Data delay time Data setup time Symbol t WCL1 t DCL2 t WCL2 t WCH t WCL t DM t DF t DD t SD Min 450 -- 900 450 450 -- -- -- 250 Typ -- -- -- -- -- -- -- -- -- Max -- 200 -- -- -- 300 300 200 -- Unit ns ns ns ns ns ns ns ns ns
Note: No load is applied to all the output terminals (MA, MB, FLM, D1, and D2).
tWCL1 1V 2 CC tDCL2 CL2 tWCL2 1V 2 CC tWCH 1V 2 CC tDM tDF tWCL
CL1
MA, MB
FLM
D1 tDD D2
1V 2 CC tSD 1V 2 CC
32
HD61830/HD61830B
HD61830B Absolute Maximum Ratings
Item Supply voltage Terminal voltage Operating temperature Storage temperature Symbol VCC VT Topr Tstg Value -0.3 to +0.7 -0.3 to VCC +0.3 -20 to +75 -55 to +125 Unit V V C C Notes 1, 2 1, 2
Notes: 1. All voltage is referred to GND = 0 V. 2. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed. We strongly recommend that you use the LSIs within electrical characteristic limits for normal operation, because use beyond these conditions will cause malfunction and poor reliability.
33
HD61830/HD61830B
HD61830B Electrical Characteristics (VCC = 5V 10%, GND = 0V, T a = -20 to +75C)
Item Input high voltage (TTL) Input low voltage (TTL) Input high voltage Input high voltage (CMOS) Input low voltage (CMOS) Output high voltage (TTL) Output low voltage (TTL) Output high voltage (CMOS) Output low voltage (CMOS) Input leakage current Three-state leakage current Pull-up current Power dissipation Notes: 1. 2. 3. 4. 5. 6. 7. 8. Symbol VIH VIL VIHR VIHC VILC VOH VOL VOHC VOLC I IN I TSL I PL PW Min 2.2 0 3.0 0.7 VCC 0 2.4 0 Typ -- -- -- -- -- -- -- Max VCC 0.8 VCC VCC 0.3 VCC VCC 0.4 VCC 0.4 5 10 20 50 Unit V V V V V V V V V A A A mW -I OH = 0.6 mA I OL = 1.6 mA -I OH = 0.6 mA I OI = 0.6 mA VIN = 0 - VCC Test Condition Notes 1 2 3 4 4 5 5 6 6 7
VCC - 0.4 -- 0 -5 -10 2 -- -- -- -- 10 --
VOUT = 0 - VCC 8 Vin = GND External clock f cp = 2.4 MHz 9 10
Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES. Applied to input terminals and I/O common terminals, except terminals SYNC and CR. Applied to terminal RES. Applied to terminals SYNC and CR. Applied to terminals DB0-DB7, WE, MA0-MA15, OE, CE, and MD0-MD7. Applied to terminals SYNC, FLM, CL1, CL2, D1, D2, MA, and MB. Applied to input terminals. Applied to I/O common terminals. However, the current which flows into the output drive MOS is excluded. 9. Applied to SYNC, DB0-DB7, and RD0-RD7. 10. The current which flows into the input and output circuits is excluded. When the input of CMOS is in the intermediate level, current flows through the input circuit, resulting in the increase of power supply current. To avoid this, input must be fixed at high or low.
34
HD61830/HD61830B
Input Terminal Applicable terminal: CS, E, RS, R/W, RES, CR (without pull-up MOS)
VCC PMOS
NMOS
Applicable terminal: RD0-RD7 (with pull-up MOS)
VCC PMOS VCC PMOS
(Pull-up MOS) NMOS
35
HD61830/HD61830B
Output Terminal Applicable terminal: CL1, CL2, MA, MB, FLM, D1, D2, WE, OE, CE, MA0-MA15
VCC PMOS
NMOS
I/O Common Terminal Applicable terminal: DB0-DB7, SYNC, MD0-MD7 (MD0-MD7 have no pull-up MOS)
VCC PMOS (Pull-up MOS) PMOS NMOS Data Input circuit NMOS VCC PMOS
VCC Enable
Output circuit (Three state)
36
HD61830/HD61830B
Timing Characteristics
HD61830B Clock Operation (V CC = 5 V 10%, GND = 0V, Ta = -20 to +75C)
Item External clock operating frequency External clock duty External clock rise time External clock fall time SYNC output hold time SYNC output delay time SYNC input hold time SYNC input set-up time Symbol f cp Duty t rcp t fcp t HSYO t DSY t HSYI t SSY Min 100 47.5 -- -- 30 -- 10 -- Typ -- 50 -- -- -- -- -- -- Max 2400 52.5 25.0 25.0 -- 210 -- 180 Unit kHz % ns ns ns ns ns ns Notes 1 1 1 1 2, 3 2, 3 2 2
Notes: 1. Applied to external clock input terminal.
Th Tl
0.7 VCC 0.5 VCC 0.3 VCC Oscillator CR trcp tfcp Duty cycle = Th Th + Tl x 100%
2. Applied to SYNC terminal.
0.7 VCC CR 0.3 VCC tDSY tHSYO SYNC (Output: at master mode) 0.7 VCC 0.3 VCC tHSYI tSSY 0.7 VCC 0.3 VCC tHSYI tSSY tDSY tHSYO
SYNC (Input: at slave mode)
3. Testing load circuit.
Test point CL CL = 30 pF (CL includes jig capacitance)
37
HD61830/HD61830B
HD61830B MPU Interface (VCC = 5V 10%, GND = 0V, Ta = -20 to +75C)
Item Enable cycle time Enable pulse width High level Low level Enable rise time Enable fall time Setup time Data setup time Data delay time Data hold time Address hold time Output data hold time Note: * Symbol t CYC t WEH t WEL t Er t Ef t AS t DSW t DDR t DHW t AH t DH Min 1.0 0.45 0.45 -- -- 140 225 -- 10 10 20 Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 25 25 -- -- 225 -- -- -- Unit s s s ns ns ns ns ns * ns ns ns
The following load circuit is connected for specification:
tCYC tWEH E 2.2V 0.8V tAS CS, R/W, RS 2.2V 0.8V tDSW DB0-DB7 (MPUHD61830B) 2.2V 0.8V tDDR DB0-DB7 (MPUHD61830B) 2.4V 0.4V tDH tDHW tEr tEf tWEL
tAH
VCC D1 Test point D2 R C D3 D4 RL = 2.4 k R = 11 k C = 130 pF (C includes jig capacitance) Diodes D1 to D4 : 1S2074 H RL
38
HD61830/HD61830B
HD61830B External RAM and ROM Interface (VCC = 5V 10%, GND = 0V, Ta = -20 to +75C)
Item MA0-MA15 delay time MA0-MA15 hold time CE delay time CE hold time OE delay time OE hold time MD output delay time MD output hold time WE delay time WE clock pulse width MD output high impedance time (1) MD output high impedance time (2) RD data set-up time RD data hold time MD data set-up time MD data hold time Notes: 1. RAM write timing
T1 CR T2 0.7 VCC 0.3 VCC tHCE CE tDMA tHMA MA0-MA15 tDOE tHOE OE tDWE WE tZMDR tDMD (High impedance) tWWE Valid data tDWE 0.6V tDMA tHMA 2.4V 0.6V tDOE tHOE 2.4V 0.6V T3 T1
Symbol t DMA t HMA t DCE t HCE t DOE t HOE t DMD t HMDW t DWE t WWE t ZMDF t ZMDR t SRD t HRD t SMD t HMD
Min -- 40 -- 40 -- 40 -- 10 -- 150 10 50 50 40 50 40
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 300 -- 300 -- 300 -- 150 -- 150 -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 2 2 2 2
2.4V 0.6V
tZMDF
MD0-MD7 (output)
2.4V 0.6V
2.4V 0.6V
tHMDW T1: Memory data refresh timing for upper screen T2: Memory data refresh timing for lower screen T3: Memory read/write timing
39
HD61830/HD61830B
2. ROM/RAM read timing
T1 T2 T3 T1
CR
a (*1) b tDCE tHCE 2.4V 0.6V tDCE tHCE (*2)
(*1) a tDCE tHCE
CE
(*2)
OE
0.6V
tDMA tHMA Address for upper screen tSMD 2.2V
tDMA tHMA Address for the lower screen tHMD tSMD tHMD
tDMA tHMA (*3) tSMD
tHMA
MA0-MA15
2.4V 0.6V
tHMD
MD0-MD7 (input)
0.8V
Data for the upper screen tSRD tHRD
Data for the lower screen tSRD tHRD
(*4)
RD0-RD7
2.2V 0.8V
Data for the upper screen
Data for the lower screen
Invalid data
This figures shows the timing for Hp = 8. For Hp = 7, time shown by "b" becomes zero. For Hp = 6, time shown by "a" and "b" become zero. Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of Hp = 8, Hp = 7, or Hp = 6 respectively. *2 The waveform for instructions with memory read is shown with a dash line. In other cases, the waveform shown with a solid line is generated. *3 When an instruction with RAM read/write is executed, the value of cursor address is output. In other cases, invalid data is output. *4 When an instruction with RAM read is executed, HD61830B latches the data at this timing. In other cases, this data is invalid. 3. Test load circuit VCC D1 Test point D2 R C D3 D4 RL = 2.4 k R = 11 k C = 50 pF (C includes jig capacitance) Diodes D1 to D4 : 1S2074 H RL
*1
40
HD61830/HD61830B
HD61830B LCD Driver Interface (VCC = 5V 10%, GND = 0V, Ta = -20 to +75C)
Item Clock cycle time Symbol t WCL2 Min 416 150 150 -- 100 100 100 100 -200 400 1000 400 1000 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 50 -- -- -- -- 200 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 2, 3 2, 3 2, 3 2, 3
Clock pulse width(high level) t WCH Clock pulse width(low level) Data delay time Data hold time Clock phase difference (1) Clock phase difference (2) Clock phase difference (3) MA, MB delay time FLM set-up time FLM hold time MA set-up time MA hold time t WCL t DD t DH t CL1 t CL2 t CL3 t DM t SF t HF t SMA t HMA
41
HD61830/HD61830B
Notes: 1.
tWCL2 tWCH CL2 0.7 VCC 0.3 VCC tCL1 CL1 tDD D1, D2 0.7 VCC 0.3 VCC tDM MA, MB 0.7 VCC 0.3 VCC tCL2 0.7 VCC 0.3 VCC t WCH tDH tCL3 tWCL
2.
CL1 tSF FLM 0.7 VCC 0.3 VCC tSMA MA 0.7 VCC 0.3 VCC tHMA 0.7 VCC 0.3 VCC tHF
3. Test load circuit Test point CL CL = 100 pF (CL includes jig capacitance)
42
HD61830/HD61830B
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
43

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